Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and note type personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that rely upon active matrix drive and are capable of presenting a high-definition display are being utilized as these liquid crystal displays devices.
The principal elements connected to one pixel of a liquid crystal display unit are illustrated schematically by an equivalent circuit diagram in FIG. 21.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 967 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other. The liquid crystal has capacitance and forms a capacitor 965 between the pixel electrode 964 and the electrode 967. Often an auxiliary capacitor 966 for assisting the capacitance of the liquid crystal is provided.
In this liquid crystal display device, the TFT 963, which has a switching function, is turned on and off under the control of a scan signal. When the TFT 963 is on, a gray-scale signal voltage that corresponds to a video data signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 967. This potential difference is held for a fixed period of time by the liquid-crystal capacitor 965 and auxiliary capacitor 966 even after the TFT 963 is turned off, as a result of which an image is displayed.
A data line 962 that sends a plurality of level voltages (gray-scale signal voltages) applied to each pixel electrode 964 and a scan line 961 that sends the scan signal are wired on the semiconductor substrate in the form of a grid. The data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel. The scan line 961 and data line 962 constitute a large capacitive load owing to the capacitance produced at the intersection of these lines and capacitance of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scan signal is supplied to the scan line 961 from a gate driver 970, and that the supply of gray-scale signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller 950, a required clock CLK and control signals are supplied from the display controller 950, and video data is supplied to the data driver 980. At the present time, video data is principally digital data. A power-supply circuit 940 supplies driving power to the gate driver 970 and data driver 980.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected successively every pixel row, that is, every line, by each scan line, and a gray-scale signal voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a binary scan signal, it is required that the data driver 980 drive the data lines by gray-scale signal voltages of multiple levels that conform to the number of gray levels. To this end, the data driver 980 has a digital-to-analog converter (DAC) comprising a decoder for converting video data to a gray-scale signal voltage and an operational amplifier for amplifying the gray-scale signal voltage and outputting the amplified signal to the data line 962.
Progress has been made in raising image quality (increasing the number of colors) in portable telephone terminals, note-type personal computers and liquid crystal TVs, etc. However, there is now growing demand for video data of six bits per each of the colors R, G, B (260,000 colors) and preferably 8-bit video data (26,800,000 colors) or higher.
For this reason, a data driver that outputs a gray-scale signal voltage corresponding to multiple-bit video data is now required to output multiple gray-scale voltages and, in addition, to produce highly accurate voltage outputs corresponding to gray-scales. If reference voltages generated in correspondence with multiple gray-scale voltages are increased, the number of elements in a reference voltage generating circuit and the number of elements of switching transistors in the decoder circuit that selects reference voltages corresponding to input video signals are increased.
Patent Document 1 proposes a technique for reducing number of reference voltages and number of switching transistors by utilizing interpolation. FIG. 23 is a diagram illustrating the configuration of a selecting circuit in a digital-to-analog converter circuit of a data driver disclosed in Patent Document 1 (FIG. 10). This arrangement uses an output amplifier circuit (interpolation amplifier) having two inputs (the amplifier is not shown). The interpolation amplifier receives OUT1 (Vn) and OUT2 (Vn+2) as inputs and produces voltages obtained by internally dividing these two inputs at a ratio of 1:1. An 8-bit input signal is divided into six bits and three bits (with one bit being overlapped) and tournament-type decoders (tournaments 1, 2, 3) are used as decoders for decoding the 6-bit signal. With regard to 8-bit display data, an input gray level of six bits (D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N, D4P, D4N, D5P, D5N) are divided into the three blocks (A, B, C) mentioned below.
Specifically, V(0), V(8), . . . V(0+8n), . . . V(248), V(256) are decoded by tournament 1; V(2), V(6), . . . V(2+4n), . . . V(250), V(254) are decoded by tournament 2; and V(4), V(4+8n), . . . V(252) are decoded by tournament 3.
A 6-bit-input first decoder (1st decoder) is constructed by tournament 1, tournament 2 and tournament 3.
Outputs VA, VB and VC of the 1st decoder are supplied to a 2-bit (D6P, D6N, D7P, D7N) second decoder (2nd decoder) through a 1-bit selecting circuit to which changeover signals D0N and D0P are applied, and two outputs OUT1(Vn), OUT2(Vn+2) are obtained. The changeover signals D0N and D0P are applied to both the 1st decoder and the 2nd decoder.
The selecting circuit selects one output from among the outputs VA, VB and VC of tournaments 1, 2 and 3, respectively, and supplies it to the 2nd decoder.
The two outputs OUT1(Vn) and OUT2(Vn+2) of the 2nd decoder are supplied to the 2-input output amplifier circuit (interpolation amplifier) (not shown).
This circuit approximately halves the number of reference voltages (gray-scale voltages) using an interpolation amplifier.
FIG. 24A is a diagram illustrating the configuration of tournament 1 shown in FIG. 23, and FIG. 24B is a diagram illustrating the configuration of tournament 3. As shown in FIG. 24A, gray-scale voltages 0+8n (V00, V08, V16, . . . V248, V256) are supplied to tournament 1, which proceeds to decode 6-bit display data (D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N, D4P, D4N, DSP, D5N) and obtain output VA. Gray-level voltages 2+4n (2, 6, 10, 14, . . . 250, 254) are supplied to tournament 2, which proceeds to decode 6-bit display data (D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N, D4P, D4N, DSP, D5N) and obtain output VB. Gray-level voltages 4+8n (V04, V12, V20, . . . V244, V252) are supplied to tournament 3, which proceeds to decode 5-bit display data (D1P, D1N, D2P, D2N, D3P, D3N, D4P, D4N, DSP, D5N) and obtain output VC.
In order to prevent deterioration of the liquid crystal, the data driver usually performs AC drive so as to apply positive and negative voltages alternatingly as the voltage VCOM of the opposing substrate electrode in the liquid crystal cell. To achieve this, positive-drive and negative-drive gray-scale voltage signals are output. FIG. 22A is a diagram illustrating the relationship between applied voltage and transmittance in normally white liquid crystal, and FIG. 22B is a diagram illustrating the relationship between gray levels of a liquid crystal display device for driving liquid crystal having the characteristic of FIG. 22A and output voltage of a data driver (voltage applied to the liquid crystal). When the voltage applied to the liquid crystal is at its highest at gray level 0 in FIG. 22B, transmittance is at its lowest (the display is black). As the gray level rises, the voltage applied to the liquid crystal falls, transmittance rises and the display approaches a white display. The relationship between the voltage applied to the liquid crystal and transmittance and the relationship between gray level and the output voltage of the data driver are non-linear characteristics, as illustrated in FIGS. 22A and 22B. The output voltage of the data driver at the time of positive drive ranges from VCOM, which corresponds to gray level 255 (eight bits), to high-potential power supply voltage VDD, which corresponds to gray level 0. At the time of negative drive, the output voltage of the data driver ranges from VCOM corresponding to gray level 255 to low-potential power supply voltage (negative power supply voltage) VSS corresponding to gray level 0.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2001-034234A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2000-183747A
[Patent Document 3] Japanese Patent Kokai Publication No. JP-P2002-043944A